FIG. 1 illustrates a conventional four transistor (4T) imager pixel 100 coupled via interconnect 125 to a conventional pixel reading circuit 150. The pixel 100 includes a photodiode 101, reset, source follower, row select, and transfer transistors 110-114, and nodes A, B, E, and P. Control signals RESET, TX, and ROW are respectively applied to the gates of the reset transistor 110, the transfer transistor 114, and the row select transistor 112. Node A is connected to a supply voltage source (VAAPIX) for the pixel 100. Node E is a charge storage node. Node P is a charge accumulation node of the photodiode 101. The outputs produced by the pixel 100 are made available at node B. These outputs include a reset output voltage Vrst and a pixel image signal output voltage Vsig. A bias circuit 113 biases a column line 125 between the pixel and a sample and hold circuit 152. The pixel reading circuit 150 includes a photo signal sample-and-hold (S/H) circuit SHS 151 for sampling and holding the Vsig output voltage, a reset signal S/H circuit SHR 152 for sampling and holding the Vrst output voltage, a differential amplifier 153, and nodes C and D. As illustrated, column line 125 couples the output of the pixel at node B to the input of the pixel reading circuit at node C.
The pixel 100 is operated by asserting the ROW control signal to cause the row select transistor 112 to conduct. The RESET control signal is asserted to cause a reset voltage from node A (e.g., VAAPIX) to be applied to charge storage node E. The RESET control signal is then deasserted. The pixel 100 outputs a reset signal Vrst through transistors 111 and 112, which is sampled and held by circuit 152. The photodiode 101 is exposed to light during a charge integration period, i.e., an exposure period. Upon completion of the integration, the accumulated charge is transferred to storage node E by transistor 114 (when TX is applied) causing the pixel 100 to output a photo signal Vsig through transistors 111 and 112 and sampled and held by circuit 151. Both the reset signal Vrst and the photo signal Vsig are output at node B, albeit at different times. During the exposure, the photodiode 101 produces a current related to the amount of incident light. Charge accumulates at node P based on the intensity of the incident light and the amount of time the transfer transistor 114 is non-conducting. When the transfer transistor 114 becomes conductive, the charge accumulated at node P is transferred through the transfer transistor 114 to storage node E.
As noted, the reset signal Vrst is sampled and held by the reset signal S/H circuit 152, while the photo signal Vsig is sampled and held by the photo signal S/H circuit 151. The sampled and held photo and reset signals are supplied as inputs to differential amplifier 153, which generates the signal (Vrst−Vsig). The resulting amplified output signal is available at node D for analog-to-digital conversion.
FIG. 2 is a block diagram of an imager 200 having a pixel array 201. Pixel array 201 comprises a plurality of pixels 100 arranged in a predetermined number of columns and rows. Each pixel 100 of array 200 may have the architecture as shown in FIG. 1 or other well-known pixel architectures.
Typically, the imager 200 is operated on a rolling shutter basis, in which the rows of pixels are turned on at different times on a rolling basis; each pixel in a selected row respectively outputs its reset Vrst and photo Vsig signals at the same time. That is, a row of pixels from the array 201 is selected by the control circuit 250 by sending a row address from the control circuit 250 to the row decoder 220. The row decoder 220 decodes the row address and operates the row driver 210. The row driver 210 asserts the ROW control signal on a line coupled to the row select transistor 112 of each pixel in the selected row.
The assertion of the ROW control signal causes the row select transistor 112 of each pixel 100 in the selected row to conduct. As previously described with respect to the processing performed within each pixel, this permits each pixel 100 in the selected row to output its reset Vrst and photo Vsig signals at node B, and for the pixel reading circuit 150 associated with each pixel to output a corresponding signal at node D. The control circuit 250 operates the column decoder 270 to cause the column driver circuit 260 to select a column from the selected pixels. The output from node D of the pixel in the selected column of the selected row is routed via node D′ to an analog to digital converter 280, which converts the output to a digital value. The digital value is processed by an image processor 290. Once the signals from each pixel of the selected row have been output, the control circuit 250 selects another row. This process is continued until every row of the array 201 has been processed. The imager 200 may include an output circuit 295 for outputting a digital signal corresponding to the complete image. The imager 200 may further include additional well known components, such as a lens assembly, which are not illustrated in order to avoid cluttering the figure.
The above described rolling shutter operation is not suitable for imaging scenes with objects having significant motion because each row is effectively imaged at a different time. In such scenes, an object may have moved significantly during the processing time between the different selected rows. Additionally, there is often a need to precisely control integration (i.e., exposure) time of a pixel on a frame basis. Control of the integration time on a frame basis would permit more accurate exposure, particularly of images having relatively bright and/or relatively dark areas. Some imagers utilize mechanical shutters, which may be difficult to control precisely. Other images utilize electronic shutters, which include storage capacitors. Although electronic shutters can be more easily controlled, the use of capacitors has some disadvantages including, for example, a decreased pixel fill factor, decreased efficiency in pixel charge transfer, and increased susceptibility to noise. Accordingly, there is a need for a pixel architecture that includes an electronic shutter control capable of operating in a full frame mode, but which is relatively immune to the known disadvantages associated with a pixel architecture featuring a capacitor.